Cartridge edge connectorsROM pinsDSP pinsMAD-1 pinsCIC - Security Chip pinsSRAM pins |
If you find more information, or find an error, let me know,
-neviksti
21.477MHz Clock 01 32 /WRAM
EXPAND 02 33 REFRESH
PA6 03 34 PA7
/PARD 04 35 /PAWR
GND 05 36 GND
F A11 06 37 A12
r A10 07 38 A13
o A9 08 39 A14
n A8 09 40 A15
t A7 10 41 BA0
A6 11 42 BA1
o A5 12 43 BA2
f A4 13 44 BA3
A3 14 45 BA4
c A2 15 46 BA5
a A1 16 47 BA6
r A0 17 48 BA7
t /IRQ 18 49 /CART
D0 19 50 D4
D1 20 51 D5
D2 21 52 D6
D3 22 53 D7
/RD 23 54 /WR
CIC out data (p1) 24 55 CIC out data (p2)
CIC in data (p7) 25 56 CIC in clock (p6)
/RESET 26 57 CPU_CLOCK
Vcc 27 58 Vcc
PA0 28 59 PA1
PA2 29 60 PA3
PA4 30 61 PA5
Left Audio Input 31 62 Right Audio Input
Definitions:
A0-A15 - address bus A (offset)
BA0-BA7 - address bus A (bank)
/RD - read control line for address bus A
/WR - write control line for address bus A
/CART - set low by console's address decoder when address bus A is accessing memory
in the cartridge region
/WRAM - set low by console's address decoder when address bus A is accessing memory
in the WRAM region
/IRQ - a cartridge can pull this low to request an IRQ interrupt on the main CPU
PA0-PA7 - address bus B
/PARD - read control line for address bus B
/PAWR - write control line for address bus B
CIC - the security chip
(referred to as CIC because that's how it's labeled on cartridge boards)
EXPAND - line is pulled high through a resistor
the only other thing this is connected to is a pin of the expansion port
(probably meant to allow cartridges to know if something is in the expansion port)
CPU_CLOCK - I believe this is either the current memory access cycle clock, or it is the
current clock given to the CPU core. I need to do more verification to be sure.
I know that a 21.477MHz signal is given to the main CPU (+peripherals) chip, and
depending on the current memory access cycle, the CPU core is actually clocked at
3.58, 2.68, or 1.79 Mhz (divided down from the original 21.477MHz).
This line connects to the main CPU (+peripherals) chip, which I believe outputs
this system frequency, probably to allow a cartridge to stay synchronized with the
CPU's memory access cycles if it needs to.
REFRESH - This is also some kind of clock I believe.
I think it is output from the MainChip and connects to the WRAM. It's probably
some kind of memory refresh signal.
Audio Inputs - whatever the cartridge puts on these lines will be mixed into the SNES's
audio output.
This seems to be consistent with all their mask ROMs (some are 32pin, others 36pin).
A17 01 32 Vcc
A18 02 31 /OE
A15 03 30 A19
A12 04 29 A14
A7 05 28 A13
A6 06 27 A8
A5 07 26 A9
A4 08 25 A11
A3 09 24 A16
A2 10 23 A10
A1 11 22 /CS
A0 12 21 D7
D0 13 20 D6
D1 14 19 D5
D2 15 18 D4
Vss 16 17 D3
or
A20 01 36 Vcc
A21 02 35 A22
A17 03 34 Vcc
A18 04 33 /OE
A15 05 32 A19
A12 06 31 A14
A7 07 30 A13
A6 08 29 A8
A5 09 28 A9
A4 10 27 A11
A3 11 26 A16
A2 12 25 A10
A1 13 24 /CS
A0 14 23 D7
D0 15 22 D6
D1 16 21 D5
D2 17 20 D4
Vss 18 19 D3
This is how most DSP chips are hooked up.
(DSP is a uPD77C25 made by NEC)
Vcc 01 28 Vcc
Vcc 02 27 register select(A14 used when DSP is mapped to cartridge memory region,
nc 03 26 /CS A12 used when DSP is mapped to expansion memory region)
nc 04 25 /RD
nc 05 24 /WR
D0 06 23 nc
D1 07 22 nc
D2 08 21 Vcc
D3 09 20 Vcc
D4 10 19 Vcc
D5 11 18 Vcc
D6 12 17 GND
D7 13 16 RESET (inverted /RESET- SNES slot)
D8 14 15 CLOCK
the MAD-1 chip
/HI 01 16 /LOW
SRAM /CS 02 15 A15 (LoRom), A13 (HiRom)
NC 03 14 BA4 (LoRom), A14 (HiRom)
ROM /OE 04 13 BA5
SRAM Vcc 05 12 Vcc or BA6 (LoRom), A15 or BA6(HiRom)...
Vcc 06 11 /CART (pad 49 on cartridge edge)
resistor to +3V of battery 07 10 GND=LoRom, Vcc=HiRom
GND 08 09 /RESET (pad 26 on cartridge edge)
/HI <--- if two ROM chips, this selects the upper one
/LOW <--- if two ROM chips, this selects the lower one
on chip label: D411
on board label: CIC
pad24 01 16 Vcc
pad55 02 15 NC
NC 03 14 NC
GND 04 13 NC
NC 05 12 NC
pad56 06 11 NC
pad25 07 10 NC
GND 08 09 NC
the 16kbit SRAM used by Nintendo
A7 01 24 Vcc
A6 02 23 A8
A5 03 22 A9
A4 04 21 /WE
A3 05 20 /OE
A2 06 19 A10
A1 07 18 /CS
A0 08 17 D7
D0 09 16 D6
D1 10 15 D5
D2 11 14 D4
Vss 12 13 D3
the 256kbit SRAM used by Nintendo A14 01 28 Vcc
A12 02 27 /WE
A7 03 26 A13
A6 04 25 A8
A5 05 24 A9
A4 06 23 A11
A3 07 22 /OE
A2 08 21 A10
A1 09 20 /CS
A0 10 19 D7
D0 11 18 D6
D1 12 17 D5
D2 13 16 D4
GND 14 15 D3